1. Field of the Invention
This invention relates to the fabrication of integrated circuits, and in particular, to the use of lift-off technology for fabricating self-aligned electrical connecting regions to integrated circuit structures.
2. Description of the Prior Art
A technique which is receiving increasing attention for the fabrication of metal connections to integrated circuits is lift-off processing. The name originates from the fact that materials which are deposited over areas of an integrated circuit where they are not needed are subsequently removed by being physically lifted from the surface of the circuit by removal of an underlying masking layer. Lift-off processing offers several advantages over conventional etching techniques commonly employed for such processes. For example, finer tolerances are achievable without radiation damage to active devices which may accompany plasma processing. The lift-off process allows high yields and is compatible with almost any desired material. Lift-off processing permits the fabrication of metal lines with well-defined contours which may be more easily overcoated with passivating material.
Typical prior art techniques for fabricating metal contacts using lift-off processing are described in: "Lift-Off Techniques for Fine Line Metal Patterning," by J. M. Frary and P. Seese, Semiconductor International, December 1981, pages 72-89, and "Polyimide Lift-Off Technology for High-Density LSI Metalization," by Y. Homma et al., IEEE Transactions on Electron Devices, Vol. ED-28, No. 5, May 1981, pages 552-556.
Conventional lift-off processes, however, suffer from several disadvantages when used to fabricate metal contacts. First, such processes are often not self-aligned, thereby requiring the use of more than one mask to define the contact area. Secondly, such prior art processes result in a non-planar upper surface of the semiconductor structure, which is more difficult to coat with subsequent layers of materials.